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Freescale Semiconductor /MKE14D7 /PORTA /GPCLR

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Interpret as GPCLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0GPWD0 (0)GPWE

GPWE=0

Description

Global Pin Control Low Register

Fields

GPWD

Global Pin Write Data
GPWE

Global Pin Write Enable

0 (0): Corresponding Pin Control Register is not updated with the value in GPWD.

1 (1): Corresponding Pin Control Register is updated with the value in GPWD.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data